DA based Efficient Parallel Digital FIR Filter Implementation for DDC and ERT Applications

Abstract – This paper discusses FPGA implementation of finite impulse response (FIR) filters using their application in Digital Down-Converters (DDCs) for software radio and in (Electrical Resistance Tomography) ERT The implementation is based on distributed arithmetic (DA) which substitute multiply and accumulate operations with a series of look-up-table (LUT) accesses. Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of pre calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed DDC is implemented in VHDL and verified via simulation. The proposed method offers average reductions of 30% in the number of LUT, 42% reduction in occupied slices and 38% reduction in the number gates needed for low pass FIR filter implementation method. The proposed DA based FIR filter can be used in electrical resistance tomography (ERT) system: it is the time delay of the filter that affects the real-time performance of the conventional ERT system. The proposed design shows 14% reduction in delay as compared to conventional logic based DA architecture. Though there is power trade off but there is significant improvement in area and delay parameters.